FIG. 6 illustrates the typical configuration of a conventional serial digital interface, also termed serialization/deserialization (SerDes), adapted for transferring data at a rate of giga-bit band. Referring to FIG. 6, in this serial digital interface, an input buffer 101 is differentially supplied with complementary received signals RXT and RXC to output a differential signal. A PLL (phase-locked loop) circuit 102 outputs a clock signal which is phase-synchronized with a system clock signal SCLK and its complementary signal SCLKB. The differential output clock signal of the PLL circuit 102 is supplied to a divider 103. This divider 103 outputs divided multi-phase clocks with respective phases thereof equally spaced each other. The multi-phase clocks from the divider 103 are supplied to a phase interpolator (phase-shift circuit) 102.
The phase interpolator 104 outputs multi-phase clocks, each phase of which corresponds to the phase obtained by internal division of the phase difference between the associated input clock signals. The multi-phase clocks output from the phase interpolator 104 are supplied to a sample circuit 105.
The sample circuit 105 includes a plurality of flip-flops, not shown, connected in parallel. The flip-flops, which receive the output signal (received data) of the input buffer 101 at data terminals thereof, and receives, as sampling clocks, corresponding ones of multi-phase clocks from the phase interpolator 104 at clock terminals thereof, latch and output the received data responsive to the respective sampling clocks.
A CDR (clock and data recovery) control circuit 106 includes an up/down counter receiving an output of a flip-flop, not shown, of the sample circuit 105, and counting up and down when an output of the flip-flop is logic 0 or logic 1, respectively. The CDR control circuit also includes a filter, not shown, for time averaging an output of the up/down counter, and a control circuit, not shown, receiving and decoding an output of the filter and transmitting a phase controlling signal (ratio of internal division of the phase interpolator 104) to the phase interpolator 104. The divider 103, phase interpolator 104, sample circuit 105 and the CDR control circuit 106 compose a clock and data recovery circuit. The clock and data recovery circuit generates and outputs received data and a recovered clock signal. Regarding the detail of the clock and data recovery circuit, reference may be made to e.g. Patent Document 1.
Out of a plural number (four in FIG. 6) of received data signals, sampled in the plural flip-flops, not shown, of the sample circuit 5, two data signals, for example odd and even bit data, are output as output data signals of the clock and data recovery circuit.
The serial data signal output from the sample circuit 105 of the clock and data recovery circuit is written in a FIFO 115. More specifically, the serial data signal is written in a register 118 of the FIFO 115, with an output of the counter 117 as a write address. 2-bit data, read out from the register 118, with an output of the counter 116 as a read address, are supplied to a serial-to-parallel converter 109 via selector 108. The serial-to-parallel converter 109 executes serial-to-parallel conversion (2:10 serial-to-parallel conversion), based on an output of the counter 110, to output 10-bit parallel received data RXDAT [9:0] to an internal circuit, not shown. A divided clock signal obtained on dividing an output of a selector 107 by the counter 110 is supplied to serial-to-parallel converter 109 as a clock signal for the serial-to-parallel conversion. This counter may, for example, be a Johnson counter. The selector 107 selects either the divided clock signal of the divider 103 or output clock signal of the phase interpolator 104, based on a selection signal Sel1, and supplies the selected signal to the counter 110. In case wherein the output clock signal of the phase interpolator 104 is supplied to the counter 110, the selector 107 may be omitted. The selector 108 selects either received serial data from the sample circuit 105 of the clock and data recovery circuit, or received serial data, transiently stored in the FIFO 115, based on the selection signal Sel1, and outputs the selected data.
A serialization circuit includes a parallel-to-serial converter 114 for converting 10-bit parallel transmission data TXDAT [9:0] into two streams of serial data, a selector 119 and a multiplexer 113 receiving an output (even and odd bits) from the selector 119 to multiplex the data by 2:1. The serialization circuit also includes a pre-emphasis circuit 112 for enhancing the signal amplitude (pre-emphasis) at each signal change point, and a differential output buffer 111 for differentially outputting the transmission signal. The selector 119 selects either the transmission serial data, output from the parallel-to-serial converter 114, for example odd/even data of two bits, or received serial data from the selector 108, for example, odd/even data of two bits, based on a selection signal (interrupt enable signal) Sel2. For example, the selector 119 selects and outputs received serial data from the selector 108, during the pass-through time, while selecting and outputting an output of the parallel-to-serial converter 114 for the merge operation, that is, in case of the selection signal Sel2 indicating interrupt enable. It is noted that the merge operation means merging the frames of the received data and the transmission data and serially transmitting the so merged frames.
In the configuration of FIG. 6, the received serial data signal is written in and read from the FIFO 115 as serial data to perform change over of the clock from received clock (output of the phase interpolator 104) to an internal clock (clock obtained on dividing an output of the PLL circuit 102 by the divider 103). The received serial data read from the FIFO 115 is converted by the serial-to-parallel converter 109 into parallel data.
In contrast thereto, in the configuration shown in FIG. 7, serial data signals (2-bit data) output from the sample circuit 105 of the clock and data recovery circuit are supplied to the serial-to-parallel converter 109, for serial-to-parallel conversion, in order to generate received 10-bit parallel data RXDAT [9:0]. The 10-bit parallel data RXDAT [9:0] from the serial-to-parallel converter 109 are written in a register 118′ of the FIFO 115 and parallel data read out from the register 118′ are supplied to a selector 120. In this configuration, the selector 120 receives 10-bit transmission parallel data TXDAT [9:0] and 10-bit parallel data, read out from the register 118′ of the FIFO 115 and, based on the selection signal (interrupt enable signal) Sel2, selects and outputs an output of the register 118 during the pass-through time, while selecting and outputting the transmission parallel data TXDAT [9:0] during interrupt enable time. A parallel output from the selector 120 is supplied to the parallel-to-serial converter 114 which performs 10:2 parallel-to-serial conversion. More specifically, the parallel-to-serial converter 114 converts the parallel 10 bits, made up of five even bits and five odd bits, into two streams of serial data of five even bits and five odd bits. The two streams of serial data from the parallel-to-serial converter 114 are supplied to the multiplexer 113 and thereby multiplexed into one stream of serial data which is supplied as an output. It is noted that, in the configuration shown in FIG. 7, the 10-bit parallel data, output from the serial-to-parallel converter 109, is written in the FIFO 115. Thus, the counter 117, generating a write address, is supplied with a signal, obtained on 10:1 frequency division of a clock signal, synchronized with received data, by a counter 110B, as a count clock. On the other hand, the counter 116, generating a read address, is supplied with a signal, obtained on 10:1 frequency division of a clock signal, synchronized with the received data, by a counter 110A, as a count clock.
Meanwhile, in Patent Document 2, there is disclosed, as a serial-to-parallel converter for transforming serial data into n-bit parallel data, a configuration including a FIFO having n-bit flip-flops and supplied with a serial data signal and a flip-flop for buffering an output of the FIFO, whereby the number of circuit elements in use may be reduced without detracting from the function.    [Patent Document 1]
Japanese Patent Kokai Publication No.JP-P2002-190724A    [Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2005-33681A